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64 Mbit SPI Serial Dual I/O Flash
A Microchip Technology Company
SST25VF064C
Data Sheet
Hold Operation
The EHLD instruction enables the hold pin functionality of the RST#/HOLD# pin. Once converted to a
hold pin, the RST#/HOLD# pin functions as a hold pin until the device is powered off and on. After the
power cycle, the pin functionality returns as a reset pin (RST#) after the power on.
The HOLD# pin is used to pause a serial sequence using the SPI flash memory, but without resetting
the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD#
mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The
HOLD mode ends when the HOLD# signal’s rising edge coincides with the SCK active low state.
If the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device
enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK active low state, then the device exits from Hold mode
when the SCK next reaches the active low state. See Figure 5 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-impedance state while SI and SCK can be V IL or V IH.
If CE# is driven high during a Hold condition, the device returns to Standby mode. As long as HOLD#
signal is low, the memory remains in the Hold condition. To resume communication with the device,
HOLD# must be driven active high, and CE# must be driven active low. See Figure 5 for Hold timing.
SCK
HOLD#
Active
Hold
Active
Hold
Active
1392 F05.0
Figure 5: Hold Condition Waveform
Write Protection
SST25VF064C provides software Write protection. The Write Protect pin (WP#) enables or disables
the lock-down function of the status register. The Block-Protection bits (BP3, BP2, BP1, BP0, and BPL)
in the status register provide Write protection to the memory array and the status register. See Table 5
for the Block-Protection description.
Write Protect Pin (WP#)
The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register.
When WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined by
the value of the BPL bit (see Table 3). When WP# is high, the lock-down function of the BPL bit is disabled.
Table 3: Conditions to execute Write-Status-Register (WRSR) Instruction
WP#
L
L
H
BPL
1
0
X
Execute WRSR Instruction
Not Allowed
Allowed
Allowed
T3.0 25036
?2011 Silicon Storage Technology, Inc.
7
DS25036A
06/11
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SST25VF064C-80-4I-S3CE 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:64 Mbit SPI Serial Dual I/O Flash
SST25VF064C-80-4I-SAE 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:64 Mbit SPI Serial Dual I/O Flash
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